Refereed Journal (SCI/SCIE Indexed):

B.V. Chandan, M.P. Bakshi, Kaushal Nigam, “Reliability optimization of dopant-free TFET performance through advanced metal layer techniques,” Microelectronics Reliability, vol. 163, pp. 115542, Oct. 2024.

Mukesh Kumar and Kaushal Nigam "Sensitivity and Non-Ideal Issues Analysis of a Dielectric Modulated Electrically Doped Junctionless TFET-Based Label-Free Biosensor," IEEE Sensor Journal, Article in Press, Jun. 2024.

Mukesh Kumar, Sajai Vir Singh, and Kaushal Nigam, "Design and Performance Analysis of Polarity Control Junctionless TFET (PC-JL-TFET)-based Biosensor," Journal of Circuits, Systems and Computers,  Article in Press, Jun. 2024.

BV Chandan, Dharmender, and Kaushal Nigam, "A Theoretical Performance and Reliability Investigation of a Vertical Hetero Oxide Based JL-TFET under Ideal Conditions," Silicon, Article in Press, Apr. 2024.

Dharmender, Kaushal Nigam, P. Yadav, and  V.A. Tikkiwal, "Performance Analysis of Dual Material Control Gate Cavity on Source Electrically Doped TFET Biosensor for Biomedical Applications," Micro & Nanostructures, Article in Press, Apr. 2024.

BV Chandan and Kaushal Nigam, "Theoretical and Simulation-based Assessment of Electrically Doped Junctionless TFET with Metal-Strip and Hetero-Material Considering Interface Trap Charges," Microelectronics Reliability, vol. 157, pp. 115393, Apr. 2024. 

 Kaushal Nigam and Dharmender, "A theoretical investigation of mole fraction-based N+ pocket doped stack oxide TFET considering ideal conditions for reliability issues," Microelectronics Reliability, vol. 155, pp. 115357, Feb. 2024. https://doi.org/10.1016/j.microrel.2024.115357

M Shreyanshi, Sangeedh, Kaushal Nigam, AS Raghuvanshi, and Dharmender, "Mole Fraction-Based Approach for Sensitivity Analysis of Dual Material Control Gate Polarity Controlled Tunnel Field Effect Transistor for Applications in Biomedical Engineering," Journal of Circuits, Systems and Computers, pp. 2450206, Jan. 2024. https://doi.org/10.1142/S0218126624502062

Kaushal Nigam, Dharmender, V.A. Tikkiwal, and MK Bind, "Theoretical Investigation of Dual-Material Stacked Gate Oxide-Source Dielectric Pocket TFET Based on Interface Trap Charges and Temperature Variations," Journal of Circuits, Systems and Computers, vol. 32, no. 15, pp. 2350252, Oct. 2023. https://doi.org/10.1142/S0218126623502523

 P Kwatra, SV Singh, and Kaushal Nigam, "Design and analysis of novel bilateral tunnelling based tunnel FET considering workfunction engineered metal strip for enhanced performance," Microelectronics Journal, vol. 139, pp. 105878, Sep. 2023. https://doi.org/10.1016/j.mejo.2023.105878

Mukesh Kumar Bind, Sajai Vir Singh,Design, and Kaushal Nigam, "Design and Investigation of the DM- PC-TFET-Based Biosensor for Breast Cancer Cell Detection," Transactions on Electrical and Electronic Materials, vol. 24, no. 01, Jul. 2023. https://doi.org/10.1007/s42341-023-00453-9

 Priyanka Kwatra, Kaushal Nigam, and Sajai Vir Singh, "Design and Performance Evaluation of a Novel Dual Tunneling based TFET Considering Trap Charges for Reliability Improvement," Silicon,  vol. 15, no. 5, pp. 2407-2425, Apr. 2023. https://doi.org/10.1007/s12633-022-02188-3

Dharmender, Kaushal Kumar Nigam, Piyush Yadav, and Amit Kumar, "Investigation of Si_1−XGe_X source dual material stacked gate oxide pocket doped hetero-junction TFET for low power and RF applications," International Journal of Electronics, vol. 111, no. 4, pp. 1-17, Feb. 2023. https://doi.org/10.1080/00207217.2023.2173804

 Mukesh Kumar Bind, Kaushal Nigam, and Sajai Vir Singh, "Sensitivity Assessment of Electrically Doped Cavity on Source Junctionless Tunnel Field-Effect Transistor-Based Biosensor," Journal of Circuits, Systems and Computers, vol. 32, no. 01, pp. 2350018, Jan. 2023. https://doi.org/10.1142/S0218126623500184

 Priyanka Kwatra, Sajai Vir Singh and Kaushal Nigam, "Performance investigation and impact of trap charges on novel lateral dual gate oxide-bilateral tunnelling based field effect transistor," Microelectronics Reliability, vol. 140, pp. 114872, Jan. 2023. https://doi.org/10.1016/j.microrel.2022.114872

 Priyanka Verma, Kaushal Nigam, and Satyendra Kumar, "Impact of gate overlap and underlap on analog/RF and linearity performance of dual-material gate-oxide-stack double-gate TFET," Applied Physics A, vol. 128, no. 11, pp. 1-17, Oct. 2022. https://doi.org/10.1007/s00339-022-06083-x

 Dharmender, Kaushal Nigam, and S Kumar, "Performance assessment of cavity on source dual material split gate GaAs/InAs/Ge junctionless TFET for label-free detection of biomolecules," Applied Physics A, vol. 128, no.10, pp. 1-12, Oct. 2022. https://doi.org/10.1007/s00339-022-06017-7

 M. K. Bind and Kaushal Nigam, "Sensitivity Analysis of Junction Free Electrostatically Doped Tunnel-FET Based Biosensor," Silicon, Springer, vol. 14, no. 13, pp. 7755-7767, Aug. 2022. https://doi.org/10.1007/s12633-021-01444-2

 Kaushal Nigam, S Kumar, and Dharmender, "Temperature sensitivity analysis of dual material stack gate oxide source dielectric pocket TFET", Journal of Computational Electronics, vol. 21, pp. 802-813, Jun.2022. https://doi.org/10.1007/s10825-022-01902-z

 KS. Singh, S. Kumar, and Kaushal Nigam, "Design and Investigation of Dielectrically Modulated Dual-Material Gate-Oxide-Stack Double-Gate TFET for Label-Free Detection of Biomolecules," IEEE Transactions on Electron Devices, vol. 68, no. 11, pp. 5784-5791, Nov. 2021. DOI: 10.1109/TED.2021.3112639

 Kaushal Nigam, S.V. Singh, and P. Kwatra, "Investigation and Design of Stacked Oxide Polarity Gate JLTFET in the Presence of Interface Trap Charges for Analog/RF Applications," Silicon, Springer, May. 2021. https://doi.org/10.1007/s12633-021-01162-9

 Nityanshi, Mathur T, Tikkiwal VA, Nigam K. "Feasibility analysis of a solar-assisted electric vehicle charging station model considering differential pricing," Energy Storage, Vol. 3, March. 2021.  https://doi.org/10.1002/est2.237

S. Kumar, Kaushal Nigam, S. Chaturvedi, AI. Khan, and A. Jain, "Performance Improvement of Double- Gate TFET Using Metal Strip Technique," Silicon, Springer, Feb. 2021. https://doi.org/10.1007/s12633-021-00982-z

 Kaushal Nigam, P.N. Kondekar, B.V. Chandan, S. Kumar, V.A. Tikkiwal, KS. Singh, E. Bhardwaj, S. Choubey, and S. Chaturvedi, "Performance and Analysis of Stack Junctionless Tunnel Field Effect Transistor," Silicon, Springer, Jan. 2021. https://doi.org/10.1007/s12633-021-00958-z

 Dharmender and Kaushal Nigam, "Low-K Dielectric Pocket and Workfunction Engineering for DC and Analog/RF Performance Improvement in Dual Material Stack Gate Oxide Double Gate TFET," Silicon, vol.13, pp.2347- 2356, Nov. 2020. https://doi.org/10.1007/s12633-020-00822-6

 S. Kumar, KS. Singh, Kaushal Nigam, and S. Chaturvedi, "Ambipolarity Suppressed Dual-Material Double Source T- Shaped Tunnel Field-Effect Transistor," Silicon, Springer, vol.13, pp. 2065-2070, Jul. 2020. https://doi.org/10.1007/s12633-020-00601-3

 KS. Singh, S. Kumar, and Kaushal Nigam, "Impact of Interface Trap Charges on Analog/RF and Linearity Performances of Dual-material Gate-oxide-stack Double-gate TFET," IEEE Transactions on Device and Materials Reliability, vol. 20, no. 2, pp. 404-412, Jun. 2020. DOI: 10.1109/TDMR.2020.2984669

 Kaushal Nigam, S. Kumar, KS. Singh, E. Bhardwaj, S. Choubey,and S. Chaturvedi, "Temperature sensitivity analysis of SGO metal strip JL TFET," IET Circuits, Devices & Systems, vol. 14, no. 4, pp. 444-449, Mar. 2020. https://doi.org/10.1049/iet-cds.2019.0412

 E. Bhardwaj, Kaushal Nigam, S. Choubey, and S. Chaturvedi, "Effect of ITCs on gate stacked JL TFET based on work-function Engineering," IET Micro & Nano letters, vol. 14, no. 12, PP. 1238-1243, Oct. 2019. https://doi.org/10.1049/mnl.2019.0252

 B.V. Chandan, Kaushal Nigam, P.N. Kondekar, and D. Sharma, "Approach to suppress the ambipolar current conduction and improve radiofrequency performance in polarity control electrically doped hetero TFET," IET Micro & Nano letters, vol. 14, no. 10, PP. 1033-1036, Sep. 2019. https://doi.org/10.1049/mnl.2018.5598

 B.V. Chandan, Kaushal Nigam, C. Rajan, and D. Sharma, "A fair comparison of the performance of charge plasma and electrostatic tunnel FETs for low-power high-frequency applications," Journal of Computational Electronics, Springer, vol. 18, no. 4, pp. 1201-1206, Aug. 2019. https://doi.org/10.1007/s10825-019-01388-2

 B.V. Chandan, Kaushal Nigam, S. Tirkey, and D. Sharma, "Metal-strip approach on Junctionless TFET in the presence of positive charge," Applied Physics A, Springer, vol. 125, no. 9, pp. 665, Aug. 2019. https://doi.org/10.1007/s00339-019-2966-1

 B.V. Chandan, Kaushal Nigam, and D. Sharma, "Approach on electrically doped TFET for suppression of ambipolar and improving RF performance," IET Circuits, Devices & Systems, vol. 13, no. 6, pp. 787-792, Jul. 2019. https://doi.org/10.1049/iet-cds.2018.5394

 Chandan, Bandi Venkata; Nigam, Kaushal; Tikkiwal, Vinay Anand; Sharma, Dheeraj; "Impact of Hetero Dielectric on the device electrical and linearity characteristics of Electrically Doped Tunnel FET," Advanced Science, Engineering and Medicine, vol 11(6), pp. 484-490(7), June 2019 https://doi.org/10.1166/asem.2019.2386

 S. Kumar, KS. Singh, Kaushal Nigam, VA Tikkiwal, and BV Chandan, "Dual-material dual-oxide double- gate TFET for improvement in DC characteristics, analog/RF and linearity performance," Applied Physics A, Springer, vol. 125 no. 5 pp. 353, Apr. 2019.   https://doi.org/10.1007/s00339-019-2650-5

 B.V. Chandan, Kaushal Nigam, D. Sharma, and VA. Tikkiwal, "A novel methodology to suppress ambipolarity and improve the electronic characteristics of polarity-based electrically doped tunnel FET," Applied Physics A, Springer, vol. 125, no. 2, pp. 81, Feb. 2019. https://doi.org/10.1007/s00339-019-2378-2

 B.V. Chandan, S Dasari, Kaushal Nigam, S. Yadav, S. Pandey, and D. Sharma, "Impact of gate material engineering on ED-Tunnel FET for improving DC/analogue-RF/linearity performances," IET Micro & Nano letters, vol. 13, no. 12, Dec. 2018. https://doi.org/10.1049/mnl.2018.5131

 B.V. Chandan, Kaushal Nigam, D. Sharma, S. Pandey, and Vinay Kumar, "Impact of a metal-strip on a polarity-based electrically doped TFET for improvement of DC and analog/RF performance," Journal of Computational Electronics, Springer, vol. 17, no. 56, pp. 1-7, Nov. 2018. https://doi.org/10.1007/s10825-018-1280-z

 Gupta, S., Sharma, D., Soni, D., Yadav, S., Aslam, M., Yadav, D.S., Nigam, K. and Sharma, N. "Examination of the impingement of interface trap charges on heterogeneous gate dielectric dual material control gate tunnel field effect transistor for the refinement of device reliability," Micro & Nano letters, Vol. 13, pp. 1192-1196, Aug. 2018. https://doi.org/10.1049/mnl.2017.0869

 B.V. Chandan, Kaushal Nigam, D. Sharma, and S. Pandey, "Impact of interface trap charges on dopingless tunnel FET for enhancement of linearity characteristics," Applied Physics A, Springer, vol. 124, no. 7, pp. 503, Jul. 2018. https://doi.org/10.1007/s00339-018-1923-8

 B.V. Chandan, Kaushal Nigam, and D. Sharma "Junctionless based dielectric modulated electrically doped tunnel FET based biosensor for label-free detection," IET Micro and Nano letters, vol. 13, no. 4, pp. 452-456, Apr. 2018.  https://doi.org/10.1049/mnl.2017.0580

Kaushal Nigam, S. Gupta, S. Pandey, D. Sharma, and P.N. Kondekar, "Controlling the ambipolarity and improvement of RF Performance using Gaussian Drain Doped TFET," International Journal of Electronics, vol. 105, no. 5, pp. 806-816, Nov. 2017. https://doi.org/10.1080/00207217.2017.1409807

Sarthak Gupta, Kaushal Nigam, S. Pandey, D. Sharma, and P.N. Kondekar, "Effect of Interface Trap Charges on Performance Variation of Heterogeneous Gate Dielectric Junctionless-TFET," IEEE Transactions on Electron Devices, vol. 64, no. 11, pp. 4731-4737, Sep. 2017. DOI: 10.1109/TED.2017.2754297

B. Raad, D. Sharma, P.N. Kondekar, Kaushal Nigam, and Sagar Baronia, "DC and analog/RF performance optimization of source pocket dual work function TFET " International Journal of Electronics, vol. 17, no. 5, pp. 1-8, jun. 2017. https://doi.org/10.1080/00207217.2017.1335788

B. Awadhiya, S. Pandey, Kaushal Nigam, and P.N. Kondekar, "Effect of ITC’s on Linearity and distortion performance Junctionless tunnel field effect transistor," Superlattices & Microstructures, Elsevier, Vol. 111, pp. 293-301, Jun. 2017. https://doi.org/10.1016/j.spmi.2017.06.036

Pulimamidi Venkatesh, Kaushal Nigam, S. Pandey, D. Sharma and P.N. Kondekar, "A dielectrically modulated electrically doped tunnel FET for application of label free biosensor," Superlattices & Microstructures, Elsevier, vol. 109, pp. 470-479, May. 2017. https://doi.org/10.1016/j.spmi.2017.05.035

Gedam, S. Tricky, Kaushal Nigam, S. Pandey, D. Sharma, and P.N. Kondekar, "Investigation of gate material engineering in junctionless TFET to overcome the trade-off between ambipolarity and RF/linearity metrics," Superlattices & Microstructures, Elsevier, vol. 109, pp. 307-315, May. 2017. https://doi.org/10.1016/j.spmi.2017.03.059

Kaushal Nigam, S. Pandey, Pawan, D. Sharma, and P.N. Kondekar, "A Barrier Controlled Charge Plasma Based TFET with Gate Engineering for Ambipolar Suppression and RF/Linearity Performance Improvement," IEEE Transactions on Electron Devices, vol. 64, no. 6, pp. 2751-2757, Apr. 2017. DOI: 10.1109/TED.2017.2693679

Kaushal Nigam, S.Pandey, P.N. Kondekar, D.Sharma, M. Verma, and A. gedam, "Performance estimation of polarity controlled electrostatically doped tunnel field effect transistor," IET Miro & Nano Letters, vol. 12, no. 4, pp. 239-244, Apr. 2017.  https://doi.org/10.1049/mnl.2016.0729

Pulimamidi Venkatesh, Kaushal Nigam, S. Pandey, D. Sharma, and P.N. Kondekar, "Impact of Interface Trap Charges on Performance of Electrically Doped Tunnel FET With Heterogeneous Gate Dielectric," IEEE Transactions on Material and Reliability, vol. 17, no. 1, pp. 245-252, Mar. 2017. DOI: 10.1109/TDMR.2017.2653620

D. Sharma, B. R. Raad, D. Yadav, P.N. Kondekar, and Kaushal Nigam, "Two-dimensional potential, electric field and drain current model of source pocket hetero gate dielectric triple work function tunnel field-effect transistor," IET Micro & Nano letters, vol. 12, no. 1, Jan. 2017. https://doi.org/10.1049/mnl.2016.0351

P.N. Kondekar, Kaushal Nigam, S. Pandey and D. Sharma, "Design and Analysis of Polarity Controlled Electrically Doped Tunnel FET with Bandgap Engineering for Analog/RF Applications," IEEE Transactions on Electron Devices, vol.64, no.2, pp. 412-418, Dec. 2016. DOI: 10.1109/TED.2016.2637638

D. Singh, S. Pandey, Kaushal Nigam, D. Sharma, D. S. Yadav and P.N. Kondekar, "A Charge Plasma Based Dielectric Modulated Junctionless TFET for Biosensor Label Free Detection," IEEE Transactions on Electron Devices, vol. 64, no. 10, pp. 271-278, Nov. 2016. DOI: 10.1109/TED.2016.2622403

Raad, D. Sharma, Kaushal Nigam, and P.N. Kondekar, "Group III–V ternary compound semiconductor materials for unipolar conduction in tunnel field-effect transistors," Journal of Computational Electronics, vol. 16, pp. 24-29, Nov. 2016.  https://doi.org/10.1007/s10825-016-0932-0

Kaushal Nigam, P.N. Kondekar, D. Sharma and B. Ram Raad , "A New Approach for Design and Investigation of Junctionless Tunnel FET using Electrically Doped Mechanism," Superlattices & Microstructures, Elsevier, vol. 98, pp. 1-7, Oct. 2016. https://doi.org/10.1016/j.spmi.2016.07.016

Kaushal Nigam, S. Pandey, P.N. Kondekar and D.Sharma, "Temperature Sensitivity Analysis of Polarity Controlled Electrostatically Doped Tunnel Field Effect Transistor," Superlattices & Microstructures, Elsevier, vol. 97, pp. 598-605, Sep. 2016. https://doi.org/10.1016/j.spmi.2016.07.023

Raad, D. Sharma, P.N. Kondekar, Kaushal Nigam, and D. S. Yadav, "Drain Work Function Engineered Doping-Less Charge Plasma TFET for Ambipolar Suppression and RF Performance Improvement: A Proposal, Design, and Investigation," IEEE Transactions on Electron Devices, vol.63, no.10, pp. 3950-3957, Aug. 2016. DOI: 10.1109/TED.2016.2600621

Kaushal Nigam, P.N. Kondekar and D. Sharma, "Approach for Ambipolar behaviour Suppression in Tunnel FET by work function Engineering," IET Micro & Nano letters, vol. 11, no. 8, pp. 460-464, Aug. 2016. https://doi.org/10.1049/mnl.2016.0178

M. Verma, D.Sharma, S.Pandey, Kaushal Nigam, and P.N. Kondekar, "Performance comparison of dual metal dielectrically modulated TFETs for the application of label free bio-sensor," Superlattices & Microstructures, Elsevier, vol. 101, pp. 219-227, Jun. 2016. https://doi.org/10.1016/j.spmi.2016.11.045

B. Raad, Kaushal Nigam, D. Sharma and P.N. Kondekar, "Performance Investigation of bandgap, gate material work function and gate dielectric engineered TFET with device reliability improvement," Superlattices & Microstructures, Elsevier, vol. 94, pp. 138-146, Jun. 2016. https://doi.org/10.1016/j.spmi.2016.04.016

Kaushal Nigam, P.N. Kondekar and D. Sharma, "High Frequency Performance of Dual Metal Gate Vertical Tunnel Field Effect Transistor Based on Work Function Engineering," IET Micro & Nano letters, vol. 11, no. 6, pp. 319- 322, Jun. 2016. https://doi.org/10.1049/mnl.2015.0526

B. Raad, D. Sharma, Kaushal Nigam and P.N. Kondekar, "A Physics Based Simulation Study of High Performance GaAsP-InGaA TFET," IET Micro & Nano letters, vol. 11, no. 7, pp. 366-368, May. 2016. https://doi.org/10.1049/mnl.2016.0050

Kaushal Nigam, P.N. Kondekar and D. Sharma, "DC Characteristics and Analog/RF Performance of Novel Polarity Control GaAs-Ge Based Tunnel Field Effect of Transistor," Superlattices & Microstructures, Elsevier, vol. 92, pp. 224-231, Apr. 2016. https://doi.org/10.1016/j.spmi.2016.01.032

B. Raad, Kaushal Nigam, D. Sharma and P.N. Kondekar, "Dielectric and work function engineered TFET for ambipolar suppression and RF performance enhancement," IET Electronic Letters, vol. 52, no. 9, pp. 770-772, Apr. 2016. https://doi.org/10.1049/el.2015.4348

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International & National Conference Proceedings:

B. V. Chandan, Dharmender, K. K. Nigam, and P.Srinivasa Subbarao “Impact of Dual Oxide on Charge Plasma-based Junctionless Tunnel Field Effect Transistor,” 2024 International Conference on Circuits and Communication Systems (ICICACS), Raichur, India, 2024, pp. 1-5. DOI: 10.1109/ICICACS60521.2024.10499180

B. V. Chandan, Dharmender and K. K. Nigam, “A Novel Approach to Enhance the Performance of TFET using Metal Strip Layer for High-Frequency Applications,” 2023 International Conference on Modeling, Simulation & Intelligent Computing (MoSICom), Dubai, United Arab Emirates, 2023, pp. 339-344. DOI: 10.1109/MoSICom59118.2023.10458819

Priyanka Kwatra, S V Singh, and Kaushal Nigam “Electrical Noise Analysis of Polarity Gate JLTFET,” 2023 9th International Conference on Signal Processing and Communication (ICSC), Noida, India, pp. 638-643, 2023. DOI: 10.1109/ICSC60394.2023.10441050

Mukesh Kumar Bind, S V Singh, and Kaushal Nigam “Design and Performance Assessment of a Si/GaSb-PC-TFET for Label-Free Bio-Sensing Applications,” 2023 9th International Conference on Signal Processing and Communication (ICSC), Nodia, India, pp. 663-668, 2023. DOI: 10.1109/ICSC60394.2023.10441362

S. Maturkar, Dharmender and Kaushal Nigam “Metal Strip Layer Approach to Enhance the DC Characteristics and Analog/RF Performance of a Dual Material Control Gate TFET,” 2023 9th International Conference on Signal Processing and Communication (ICSC), Nodia, India, pp. 732-737, 2023. DOI: 10.1109/ICSC60394.2023.10441558

B. V. Chandan, Dharmender, P. S. Subbarao and Kaushal Nigam “Examination of Interface Trap Charges on Electrically Doped Tunnel FET in the Presence of High-K Dielectric,” 7th International Conference on Electronics, Materials Engineering & Nano-Technology (IEMENTech), Kolkata, India, 2023, pp. 1-6, DOI: 10.1109/IEMENTech60402.2023.10423461

Sangeedh, A. S. Raghuvanshi, Dharmender, M. Shreyanshi and K. K. Nigam, “Investigation of DC Performance of TFET using Dielectric Pocket at Source and Drain Side,” 2023 First International Conference on Advances in Electrical, Electronics and Computational Intelligence (ICAEECI), Tiruchengode, India, 2023, pp. 1-8, DOI: 10.1109/ICAEECI58247.2023.10370834

Priyanka Kwatra, Kaushal Nigam, Sajai Vir Singh, “Performance Analysis and Design of Hetero-Dielectric Heterojunction JLTFET with Impact of Interface Traps for Analogue and RF Applications,” 2022 8th International Conference on Signal Processing and Communication (ICSC), pp. 638-643, Dec. 2022. DOI: 10.1109/ICSC56524.2022.10009288

Mukesh Kumar Bind, Kaushal Nigam, Sajai Vir Singh, “Polarity Control SiGeSource Tunnel Field Effect Transistor-based Biosensor for Bio-sensing Applications,” 2022 8th International Conference on Signal Processing and Communication (ICSC), pp. 648-652, Dec. 2022. DOI: 10.1109/ICSC56524.2022.10009309

Satyendra Kumar, Km Sucheta Singh, Kaushal Nigam, “Negative Capacitance FET for Ultra Low Power Applications: A Review,” 2022 8th International Conference on Signal Processing and Communication (ICSC), pp. 630-633, Dec. 2022. DOI: 10.1109/ICSC56524.2022.10009159

KS. Singh, S. Kumar, and Kaushal Nigam, “Vertical Tunneling Based Dual material Double gate TFET,” 2021 International Conference on Computing, Communication, and Intelligent Systems (ICCCIS), Greater Noida, India, pp. 900-904, Feb. 2021. DOI: 10.1109/ICCCIS51004.2021.9397208

Km Sucheta Singh, Satyendra Kumar, Kaushal Nigam, “Tunnel Field Effect Transistor Based Biosensors: A Review,” 2021 7th International Conference on Signal Processing and Communication (ICSC), pp. 391-395, Nov. 2021. DOI: 10.1109/ICSC53193.2021.9673155

Dharmender, Kaushal Nigam, Satyendra Kumar, “III-V/Si Heterojunction based Dual Material Stack Gate Oxide TFETs for Low Power Applications,” 2021 7th International Conference on Signal Processing and Communication (ICSC), pp. 330-336, Nov. 2021. DOI: 10.1109/ICSC53193.2021.9673374

Priyanka Kwatra, Kaushal Nigam, Sajai Vir Singh, “Performance Analysis of Novel Heterojunction ESDG-TFET for Analogue/RF Applications,” 2021 7th International Conference on Signal Processing and Communication (ICSC), pp. 336-371, Nov. 2021. DOI: 10.1109/ICSC53193.2021.9673492

Priyanka Verma, Satyendra Kumar, Kaushal Nigam, “Performance Analysis of Stack Gate Oxide Underlap TFET Utilising Metal Strip Mechanism,” 2021 7th International Conference on Signal Processing and Communication (ICSC), pp. 372-376, Nov. 2021. DOI: 10.1109/ICSC53193.2021.9673444

D. Nishad, Kaushal Nigam, V.A. Tikkiwal, and S. Kumar, “Performance Analysis of Double Gated GaAs-Ge Based Hetero Tunnel Field Effect Transistor,” 2020 6th International Conference on Signal Processing and Communication (ICSC), Noida, India, pp. 284-287, DOI: 10.1109/ICSC48311.2020.9182722, Nov. 2020. DOI: 10.1109/ICSC48311.2020.9182722

KS. Singh, S. Kumar, Kaushal Nigam, and V.A. Tikkiwal, “Tunnel Field Effect Transistor for Ultra Low Power Applications: A Review,” 2019 International Conference on Signal Processing and Communication (ICSC), Noida, India, pp. 286-291, Dec. 2019. DOI: 10.1109/ICSC45622.2019.8938260

S. Gupta, Kaushal Nigam, S. Pandey, D. Sharma, and P.N. Kondekar “Performance improvement of heterojunction double gate drain overlapped TFET using Gaussian doping,” Energy Efficient Electronic Systems and Steep Transistors Workshop (E3S), 2017 Fifth Berkeley Symposium, Berkeley, CA, USA, pp. 3, Jan. 2018. DOI: 10.1109/E3S.2017.8246171

B. V. Chandan, K. Nigam, S. Pandey, D. Sharma and P. N. Kondekar, “Temperature sensitivity analysis on analog/RF and linearity metrics of electrically doped tunnel FET,” 2017 Conference on Information and Communication Technology (CICT), Gwalior, India, 2017, pp. 1-5. DOI: 10.1109/INFOCOMTECH.2017.8340625

Kaushal Nigam, S. Pandey, P.N. Kondekar and D. Sharma, “Temperature Sensitivity Analysis of Polarity Controlled Electrically Doped Hetero-TFET,” 12th conference on Ph.D. Research in Microelectronics and Electronics (PRIME) - pp. 1- 4, 2016. DOI: 10.1109/PRIME.2016.7519465

S. Baronia, Kaushal Nigam, D. S. Yadav, Dheeraj Sharma, B. Ram Raad and Pravin Kondekar, “A Novel Approach of PNPN Dual Metal Double Gate Tunnel Field Effect Transistor for Improving DC Characteristics,” IEEE international conference on advanced communication control and computing technologies, pp. 44-47, Dec. 2016. DOI: 10.1109/ICACCCT.2016.7831597

S. Pandey, P N Kondekar, Kaushal Nigam, and D. Sharma, “A 0.9V, 3.110.6 GHz CMOS LNA with high gain and wideband input match in 90 nm CMOS process,” IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), pp. 730-733, 2016. DOI: 10.1109/APCCAS.2016.7804079

Book Chapter :

A. Gedam, S. Pandey, S. Yadav, K. K. Nigam, D. Sharma and P.N. Kondekar “Realization of Junctionless TFET-Based Power Efficient 6T SRAM Memory Cell for Internet of Things Applications,” In book: Proceedings of First International Conference on Smart System, Innovations and Computing, Jan. 2018. DOI: 10.1007/978-981-10-5828-8_49